The present invention relates, in general, to a semiconductor nonvolatile memory device, each constituted by a transistor, which is electrically programmable and erasable with respect to each threshold voltage, and more particularly to a semiconductor nonvolatile memory device in which the electrically programmable and erasable operation for a threshold is performed by applying repeatedly a plurality of pulses.
A semiconductor nonvolatile memory device having one transistor/cell structure which is capable of erasing the storage contents collectively is called "a flash memory". Since in the flash memory, from the viewpoint of its structure, an area occupied for 1 bit is small and the high integration can be realized, in recent years, the flash memory has received much attention, and the research and development of the structure and driving method thereof have been actively performed. For example, in JP-A-2-289997, there is disclosed the operation for lowering each threshold of a semiconductor nonvolatile memory device, i.e., memory cells, which performs the electrically programmable and erasable operation (programmable operation), i.e., an erase mode. The erase mode is an operation mode wherein the electric charges accumulated in a floating gate are discharged by utilizing the Fowler-Nordheim tunnel phenomenon. The threshold characteristics relating to that operation mode are shown in FIGS. 2 to 4. As shown in those Figures, the variation of the threshold with time in the logarithmic scale shows approximately a straight line after a certain lapse of time.
The threshold of the memory cell after completion of the electrically erasing operation should lie between the lower limit voltage of a power source voltage (Vccmin) and 0 V. Unlike the threshold voltage in the thermally equilibrium state in the case where the storage contents are erased by using the ultraviolet rays as in the EPROM, each threshold of the semiconductor nonvolatile memory device which performs the electrically erasing operation may go to a negative voltage while the electrically erasing operation is continued to be performed. In the case where the threshold of the memory cells is lowered to a negative voltage, the read operation and the like are adversely affected. For example, in the read operation, in the case where the threshold of the memory cells, connected to unselected word lines which are at a voltage of 0 V, lowered to the negative voltage, if the desired data line is selected, the memory current (the non-selection leakage current) is necessarily caused to flow into that data line. As a result, a time delay occurs in the read operation and a misread operation, in turn, may be caused in some cases. In order to prevent the time delay and the misread operation from occurring, conventionally, the erase operation was performed by applying repeatedly the erasing pulses in several times, and also it was verified that after completion of the erase operation, the threshold of the memory cells was equal to or higher than 0 V.
The algorithm of the conventional erase mode will hereinafter be described with reference to a flowchart of FIG. 35.
As shown in FIG. 35, prior to the erase operation, a prewrite processing 11 is executed. By the prewrite processing, it means the operation in which in order to prevent the threshold voltage (e.g., about 1 V) of the unwritten memory cells from being dropped down to the negative voltage due to the erase operation, the write operation is previously performed for all the memory cells.
In the prewrite processing 11, firstly, an initial address is set (Step 111), and then the write operation is performed for that address (Step 112). Then, it is judged whether or not that address is a final address (Step 113). Then, in the case where as a result of the judgement in Step 113, it is ascertained that that address is not the final address, after the address is incremented (Step 114), the processing is returned to Step 112 and the write operation is performed for the incremented new address. The loop of Steps 112, 113 and 114 is repeated until it is judged in Step 113 that the address of interest is the final address.
As a result of the judgement in Step 113, in the case where it is ascertained that the address of interest is the final address, the prewrite processing 11 is completed and then the processing of setting an address in Step 12 is performed.
After the initial address to be erased is set in Step 12, an erase pulse is generated and then the erase operation is performed for all the memory cells (Step 131). After completion of the erase operation, a state read operation, i.e., a verify operation, for judging whether or not the threshold of the memory cells reaches an erase threshold is performed (Step 132). In the verify operation, in the case where the threshold of the memory cell corresponding to a certain address does not reach the erase threshold, the processing is returned to Step 131 again and then the erase operation is repeatedly performed for all the memory cells (in a repetitive loop 13). In the verify operation in the repetitive loop 13, the judgement of the threshold is performed again from the same address. The loop of Steps 131 and 132 is repeatedly performed until it is judged in Step 132 that the threshold of the memory cell reaches the erase threshold.
In the case where it is judged in Step 132 that the threshold of the memory cell reached the erase threshold, it is judged whether or not the address of interest is the final address (Step 14). Then, as a result of the judgement in Step 14, in the case where it is ascertained that the address of interest is not the final address, after the address of interest is incremented (Step 15), the processing is returned to the verify operation in Step 132 again.
In the case where as a result of the judgement in Step 14, it is ascertained that the address of interest is the final address, it is judged that the threshold of all the memory cells had become the erase threshold, and then the erase mode is completed.
In the erase mode in the prior art as described above, the pulse width in the erase operation which is repeatedly performed is fixed.
In the above-mentioned prior art, it was assumed that the pulse width in the erase operation which was repeatedly performed in the erase mode was always fixed. In addition, in the case where the storage contents of the memory cells are erased, for example, as shown in FIG. 2, the characteristics of the threshold with time in the logarithmic scale show approximately a straight line. Therefore, in the case where the erase pulse width is fixed, the variation quantity of the memory threshold relative to each pulse is decreased as the number of erase operations further increases. As a result, there arises the problem that the time required for switching between the erase operation and the verify operation, and the verify operation itself become the overhead time, and as a result, the erase mode time is necessarily increased.
In addition, in the case where the control of the electrically programmable and erasable operation is executed by a central processing unit (a CPU) of a system located outside the semiconductor nonvolatile memory device, e.g., a portable system such as an automatically controlled camera system, a portable recorder or a pocket computer, there arise the problems that control of such an electrically programmable and erasable operation needs to be performed without separation of the buses between the semiconductor nonvolatile memory device and the external system and thus such a control becomes complicated, and in addition thereto, during that control operation, the CPU is occupied by the electrically programmable and erasable control of the semiconductor nonvolatile memory device.